The Pentium II incorporated the features of its older designs and added a number of enhancements. Among these are:
- Multiple Branch Prediction: predicts program execution through several branches, accelerating the flow of work to the processor.
- Data-flow Analysis: Creates an optimized, reordered schedule of instructions by analyzing data dependencies between instructions.
- Speculative Execution: Carries out instructions speculatively and, based on this optimized schedule, ensures that the processor's superscalar execution units remain busy, boosting overall performance.
- Single-edge connector (SEC) cartridge packaging: Developed by Intel, this enables high-volume availability and offers improved handling protection and a common form factor for future high-performance processors. This development resolved problems caused when pins were accidentally bent during installation or removal of CPUs.
- High-performance Dual Independent Bus (DIB) architecture (system bus and cache bus).
- System bus that supports multiple outstanding transactions to increase bandwidth availability. It also provides "glueless" support for up to two processors. This enables low-cost, two-way symmetric multiprocessing, providing a significant performance boost for multitasking operating systems and multithreaded applications. Many inexpensive motherboards offer two Slot 1 sockets, making it easy to build a dual processor system for use with operating systems like Windows NT or 2000.
- 512-KB unified, nonblocking, L2 cache: Improves performance by reducing average memory access time and providing fast access to recently used instructions and data. Performance is enhanced through a dedicated 64-bit cache bus. The speed of the L2 cache scales with the processor core frequency. This processor also incorporates separate 16-KB, L1 caches: one for instructions and one for data.
- Models available in 450, 400, and 350 MHz: Support memory caches for up to 4 GB of addressable memory space.
- Error correction coding (ECC) functionality on the L2 cache bus: for applications in which data intensity and reliability are essential.
- Pipelined floating-point unit (FPU): supports the 32-bit and 64-bit formats specified in IEEE (Institute of Electrical and Electronics Engineers) standard 754, as well as an 80-bit format.
- Parity-protected address/request and response system bus signals, with a retry mechanism for high data integrity and reliability.
Variations on a Theme: The Intel Celeron CPUs
As it had in the past, Intel faced competitors who sold CPUs with similar performance at lower prices. Most high-priced desktop computers and servers were sold with a Pentium of one sort or another, but home and entry-level were another matter. Enter a variation of the SX concept-the Celeron.
Models available in 500, 466, 433, 400, 366, and 333 MHz have expanded Intel processing into the market for computers selling under $1,200.
All the Intel Celeron processors are available in PGA packages. The versions operating at 433, 400, 366, 333, and 300A MHz are also available in single-edge processor packages.
Key features include:
- MMX media enhancement technology.
- Dynamic Execution Technology.
- A 32-KB (16-KB/16-KB) nonblocking, L1 cache for fast access to heavily used data.
- Celerons operating at 500, 466, 433, 400, 366 and 333 MHz include integrated 128-KB L2 cache.
- All Celeron processors use the Intel P6 microarchitecture's multitransaction system bus at 66 MHz. Processors at 500, 466, 433, 400, 366 and 333 MHz use the Intel P6 microarchitecture's multitransaction system bus with the addition of the L2 cache interface.
- Like the Pentium family, the Celerons offer multiple branch prediction, data-flow analysis, and speculative execution.
Figure 4.12 Intel Pentium II in SEC Package